Complementary metal-oxide semiconductor (“CMOS”) field-effect transistors (“FETs”) are employed in almost every electronic circuit application, such as signal processing, computing, and wireless communications. CMOS FETs have a gate that controls the flow of electrical current between the source and drain. Scaling down the gate length of both N-channel FETs (NFETs) and P-channel FETs (PFETs) in CMOS circuits to shorter dimensions leads to increased CMOS circuit speed. However, detrimental short-channel effects lead to high off-state leakage currents in CMOS devices, thereby increasing the power consumption. In case of extreme short-channel effects, CMOS circuits fail to operate.
FETs with multiple gates built on narrow bodies, such as, fin-shaped field effect transistors (“FinFETs”) and trigates have better electrostatic integrity than thick-body partially-depleted silicon-on-insulator (“PDSOI”) devices. However, narrow body devices on silicon-on-insulator (“SOI”) suffer from high series resistance due to loss of doping from thin extension regions into the buried oxide (“BOX”).
A known method to solve the doping loss problem is the use of advanced anneal techniques, such as millisecond laser spike anneal (“LSA”) and flash anneal (“FLA”). These anneal techniques have a very small time scale to avoid dopant diffusion, and therefore, doping loss, and yet achieve high temperatures to electrically activate the dopants. Since very low energy implants are needed for thin body devices to avoid amorphization of the thin extension regions, the lack of any implant diffusion during LSA and FLA leads to very steep extension doping profiles with high chemical concentration exceeding the solid solubility limit near the surface of the thin extension region. Therefore, a significant fraction of the implanted dose, although present in the thin extension region, is not electrically active. Even though the thin-extension sheet resistance is significantly lowered upon using LSA/FLA instead of conventional spike rapid thermal annealing (“RTA”), it is not low enough and makes the FET series resistance high compared to that of PDSOI devices.
Therefore, a new method is desired where one can create an extension doping profile that is uniform in the thin extension region and does not suffer from doping loss to the BOX.